This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-301068, filed Sep. 29, 2000, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates generally to semiconductor devices, and more particularly to a semiconductor device for use in an industrial or a railway power converter apparatus, such as an IGBT (Insulated Gate Bipolar Transistor) module to be used with a large current and a high voltage.
2. Description of the Related Art
FIG. 1 is a cross-sectional view of a prior-art IGBT module
An IGBT module 10, as shown in FIG. 1, comprises a base plate 11, a ceramic substrate 12, an IGBT chip 13, an emitter terminal 14-1, a collector terminal 14-2, a gate terminal 14-3, a resin case 15, and a resin cap 16.
A copper plate 17 is provided on a back face of the insulative ceramic substrate 12. The copper plate 17 is attached to the base plate 11 by means of a solder 18. The ceramic substrate 12 has copper plates 19-1 to 19-3 on its upper surface, which serve as emitter, collector and gate wiring elements, respectively.
A lower surface (i.e. a semiconductor substrate surface; a collector region formation surface) of the IGBT chip 13 is attached to the collector wiring element 19-2 by means of a solder 18. An emitter region present on an upper surface of the IGBT chip 13 is connected to the emitter wiring element 19-1 by means of a bonding wire 20. In addition, a gate region present on the upper surface of the IGBT chip 13 is connected to a gate resistor 21 by means of a bonding wire 20. The gate resistor 21 is bonded to the gate wiring element 19-3 by means of a solder 18.
The emitter, collector and gate terminals 14-1 to 14-3 are bonded to the emitter, collector and gate wiring elements 19-1 to 19-3 by means of solders 18.
The base plate 11 is put in the resin case 15. The upper portion of the resin case 15 is sealed by the resin cap 16. A resin 22 is filled in the space defined by the resin case 15 and resin cap 16.
FIG. 2A is a plan view of a prior-art IGBT module with a plurality of IGBT chips.
An emitter wiring element 19-1, as shown in FIG. 2A, has a T-shape and is provided on a central region of the ceramic substrate 12. A collector wiring element 19-2 is provided on the ceramic substrate so as to surround the emitter wiring element 19-1. Gate wiring elements 19-3 are provided on outer peripheral regions of the emitter wiring element 19-2. Emitter sense wiring elements 19-4 are provided on the ceramic substrate 12, adjacent to the gate wiring elements 19-3.
On the collector wiring element 19-2, four IGBT chips 13-1 to 13-4 and two FRD (Fast Recovery Diode) chips 23-1 and 23-2 are provided. Emitter/gate regions of the IGBT chips 13-1 to 13-4 are connected to the emitter/gate wiring elements 19-1 and 19-3 by means of bonding wires 20. The FRD chips 23-1 and 23-2 have their lower surfaces (semiconductor substrate surfaces; cathode regions) bonded to the collector wiring element 19-2, and have their upper surfaces (anode regions) connected to the emitter wiring element 19-1 by means of bonding wires 20. Emitter and collector terminals 14-1 and 14-2 are provided on regions ET and CT of the emitter and collector wiring elements 19-1 and 19-2, respectively.
FIG. 2B is a plan view of another prior-art IGBT module with a plurality of IGBT chips. In the structure shown in FIG. 2B, the lengths of current paths between the collector terminal 14-2 and emitter terminal 14-1 are made uniform for the respective IGBT chips.
In FIG. 2B, compared to FIG. 2A, the current paths between the emitter regions of the IGBT chips 13-3 and 13-4 chips and the emitter terminal are made longer. Thereby, the current path lengths between the IGBT chips 13-1 to 13-4 and the emitter terminal are made uniform, and the parasitic inductance, which is parasitically present in the current paths, is made uniform.
A semiconductor device comprising:
an insulative substrate having a first wiring element on a surface thereof;
a semiconductor chip provided on the first wiring element;
an insulative resin provided on the first wiring element and covering at least edge portions of the semiconductor chip, and
an insulative sealing member, provided on the insulative substrate, for covering the semiconductor chip and the insulative member, the sealing member having lower insulation properties than a region of the insulative member, which is in contact with the semiconductor chip and the first wiring element.